NXP Semiconductors /LPC408x_7x /SYSCON /PLLCFG0

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Interpret as PLLCFG0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MSEL0PSEL 0RESERVED

Description

PLL0 Configuration register

Fields

MSEL

PLL Multiplier value. Supplies the value “M” in the PLL frequency calculations. Note: For details on selecting the right value for MSEL see Section 3.10.4.

PSEL

PLL Divider value. Supplies the value “P” in the PLL frequency calculations. Note: For details on selecting the right value for PSEL see Section 3.10.4.

RESERVED

Reserved. Read value is undefined, only zero should be written.

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